2. Field of the Invention
The invention relates to static MOS random access memories.
2. Brief Description of the Prior Art
Static MOS RAM's are commonly implemented utilizing six transistor storage cells. For example, see U.S. Pat. No. 3,594,736. The six-transistor storage cells are each comprised of cross-coupled back-to-back inverters. The outputs of each inverter are also connected, respectively, to two isolation MOSFETs. Each isolation MOSFET is coupled, respectively, to a separate sense-write conductor which has a substantial parasitic capacitance associated therewith. In a memory system, each sense-write conductor is coupled to the source of a separate termination MOSFET. Each termination MOSFET has its gate and source connected to a V.sub.DD conductor. Each of the storage cells is coupled between V.sub.DD and ground. In order to obtain low cost semiconductor RAMs, it is necessary that the storage cells be as small in size as possible. This requirement prevents the respective storage cells from being able to sink much sense current when they are selected during a read operation. At the beginning of a read operation, the two sense-write conductors coupled to the selected cell should both be at voltages equal to approximately one MOSFET threshold voltage drop below V.sub.DD in order to avoid the next selected storage cell having the same state written into it as was written into the last selected storage cell during the just completed write cycle. In order to avoid the information stored in the next storage cell from being destroyed, the read cycle following a write cycle must not begin until the sense-write lines have recovered from the previous write cycle. The sense-write conductor which was driven to approximately zero volts during the write cycle recovers by being charged up through its termination MOSFET. But the termination MOSFETs are normally designed to be high impedance devices in order to avoid loading the write circuit during writing and to avoid loading the selected storage cell during sensing. Consequently, the access times of MOS static random access memories are relatively slow.